1. Field of the Invention
The present invention relates to solder pads of a package, and more particularly, to solder pads for improving reliability of a package.
2. Description of the Prior Art
High performance microelectronic devices often use solder balls or solder bumps for electrically and mechanically interconnection to other microelectronic devices. For instance, a very large scale integration (VLSI) chip may be connected to a circuit board or other next level packaging substrate by using solder balls or solder bumps. This connection technology is also referred to as “flip chip” technology. The flip chip technology is an area array connection technology and includes reflowing a body of solder onto a bond pad to form a solder bump, so as to electrically connect an IC die to a packaging board. The flip chip can break through limitations of traditional wire bonding, and the electrical performance is effectively improved due to a shorter connection pass.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art package. As shown in FIG. 1, a package 10 comprises a chip 12 and a substrate 18. The chip comprises a plurality of solder bump pads respectively connecting to the corresponding solder bumps 16. The solder bump pads 14 connect to the substrate 18 by using the solder bumps 16. In addition, an underfill layer 20 is filled in a gap between the chip 12 and the substrate 18 for tightly connecting the chip 12 with the substrate 18.
According to the prior art package technology, the substrate 18 comprises a plastic (organic) substrate or a ceramic substrate. However, a price of the ceramic substrate is high and a source of the ceramic substrate is limited, so that the plastic substrate with a low price and plentiful sources has become a mainstream material used in packages. Nevertheless, a problem of non-uniform thermal stress always occurs in a package when using the plastic substrate. For example, a coefficient of thermal expansion of the chip 12 is approximately equal to 2.7 ppm/° C., and a coefficient of thermal expansion of the plastic substrate 18 is approximately equal to 17 ppm/° C. Because the chip 12 and the plastic substrate 18 have different coefficients of thermal expansion, a variation of ambient temperature deforms the package, and moreover, the products may fail.
Please refer to FIG. 2(A) and FIG. 2(B). FIG. 2(A) and FIG. 2(B) are a schematic diagrams for illustrating deformation of a package due to a variation of ambient temperature. As mentioned above, the coefficient of thermal expansion of the plastic substrate 18 is larger than that of the chip 12. When ambient temperature rises, the package 10 is bended upwards due to over expansion of the plastic substrate 18, as shown in FIG. 2 (A). Conversely, when ambient temperature falls, the package 10 is bended downwards because the plastic substrate 18 shrinks more than the chip 12 does, as shown in FIG. 2(B). Noticeably, a periphery region of the chip 12 is a region with high thermal stress. As a result, the deformation of the periphery region is more serious than the deformation of the central region of the chip 12, which further leads to forming cracks in the package.
For preventing deformation of the package due to a thermal stress, arrangement of the solder bump pads 14 for connecting the chip 12 with the substrate 18 is changed according to the prior art method. That is, positions of the solder bumps 16 are changed to adjust stress distribution on the chip 12 and the substrate 18. Please refer to FIG. 3 and FIG. 4. FIG. 3 and FIG. 4 are schematic diagrams of the solder bump pads located on the surface of the chip. Generally, the solder bump pads are arranged in a matrix on the chip. For explaining the relationship between positions of the solder bump pads and the stress on the chip, FIG. 3 and FIG. 4 only show solder bump pads located on the region of the chip with high stress (i.e. periphery region). As shown in FIG. 3, the solder bump pads 14 are arranged in a matrix on the chip 12. When ambient temperature varies, the largest thermal stress always occurs on a position of the chip 12 with a maximum distance to neutral point (max DNP). For example, the solder bump pads 22 located at the four corners of the chip 12 are suffered with higher thermal stress, so that the package forms cracks most easily on the positions of the solder bump pads 22. As shown in FIG. 4, the solder bump pads 22 are directly removed to solve the above-mentioned problem according to the prior art method. That is, it is avoided to locate the solder bump pads and the solder bumps at the corners of the chip 12, which is called a bump corner design rule.
As mentioned above, the prior art method removes the solder bump pads 14 located at the four corners of the chip 12. However, the solder bump pads 14 on other high stress regions of the chip 12 are not removed. For example, the solder bump pads 24 shown in FIG. 4 also suffer from higher stress. As a result, as the chip 12 becomes larger, the above-mentioned method cannot effectively solve the thermal stress problem, and thus, reliability of the package is reduced.